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rev. b one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. AD7722 16-bit, 195 ksps cmos, - adc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. functional block diagram av dd dv dd ref1 a gnd dgnd v in (+) v in (? p/ s ref2 xtal clkin uni db15 db14 cal reset sync cs dval/ rd cfmt/ drdy db3/ tsi db4/ doe db5/ sfmt db6/ fsi db7/ sco db8/ sdo 16-bit a/d converter - modulator fir filter clock circuitry control logic db13 AD7722 2.5v reference db12 db11 db10 db9/fso db0 db1 db2 features 16-bit - adc 64 oversampling ratio up to 220 ksps output word rate low-pass, linear phase digital filter inherently monotonic on-chip 2.5 v voltage reference single-supply 5 v high speed parallel or serial interface general description the AD7722 is a complete low power, 16-bit, - ? adc. the part operates from a 5 v supply and accepts a differential input voltage range of 0 v to +2.5 v or 1.25 v centered around a common-mode bias. the AD7722 provides 16-bit performance for input bandwidths up to 90.625 khz. the part provides data at an output word rate of 195.3 khz. the analog input is continuously sampled by an analog modula- tor, eliminating the need for external sample-and-hold circuitry. the modulator output is processed by two finite impulse response (fir) digital filters in series. the on-chip filtering reduces the external antialias requirements to first order, in most cases. the group delay for the filter is 215.5 s, while the settling time for a step input is 431 s. the sample rate, filter corner frequency, and output word rate are set by an external clock that is nominally 12.5 mhz. use of a single bit dac in the modulator guarantees excellent linearity and dc accuracy. endpoint accuracy is ensured on-chip by calibration. this calibration procedure minimizes the zero- scale and full-scale errors. conversion data is provided at the output register through a flex- ible serial port or a parallel port. this offers 3-wire, high speed interfacing to digital signal processors. the serial interface operates in an internal clocking (master) mode, whereby an internal serial data clock and framing pulse are device outputs. additionally, two AD7722s can be configured with the serial data outputs connected together. each converter alternately transmits its conver- sion data on a shared serial data line. the part provides an accurate on-chip 2.5 v reference. a reference input/output function is provided to allow either the internal reference or an external system reference to be used as the reference source for the part. the AD7722 is available in a 44-lead mqfp package and is specified over the industrial temperature range of C 40 c to +85 c.
rev. b e2e AD7722especifications 1 (av dd = av dd1 = 5 v 5%; dv dd = 5 v 5%; agnd = agnd1 = dgnd = 0 v; uni in in u niiiin uni in c in in in in sn d i i cin d i i cin s d r i i cin u uni in in in sn d i d i s d r i i d c crr in in c d r r c s n inus s i s in in uni in r r u uni in r i in in dd i s c i s r d cin d i i cin cc cin s r rrnc r r d c r i r r r u i r r r d c u r r i i r nd cin r r r r sic rrnc r d n s i n s c sr c sr d s c d r i i r r nd u s c s c
rev. b AD7722 e3e a version parameter test conditions/comments min typ max unit logic inputs (excluding clkin) v inh , input high voltage 2.0 v v inl , input low voltage 0.8 v clock input (clkin) v inh , input high voltage 4.0 v v inl , input low voltage 0.4 v all logic inputs i in , input current v in = 0 v to dv dd 10 a c in , input capacitance 10 pf logic outputs v oh , output high voltage |i out | = 200 a 4.0 v v ol , output low voltage |i out | = 1.6 ma 0.4 v power supplies av dd , av dd1 4.75 5.25 v dv dd 4.75 5.25 v i dd total from av dd a nd dv dd 75 ma power consumption 375 mw notes 1 operating temperature range is ? 40 c to +85 c (a version). 2 measurement bandwidth = 0.5 f s ; input level = ? 0.05 db. 3 t a = 25 c to 85 c/t a = t min to t max . 4 applies after calibration at temperature of interest. 5 gain error excludes reference error. the adc gain is calibrated w.r.t. the voltage on the ref2 pin. specifications subject to change without notice.
rev. b e4e AD7722 absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . ? 0.3 v to +7 v av dd , av dd1 to agnd . . . . . . . . . . . . . . . . . . ? 0.3 v to +7 v av dd , av dd1 to dvdd . . . . . . . . . . . . . . . . . . . ? 1 v to +1 v agnd, agnd1 to dgnd . . . . . . . . . . . . . ? 0.3 v to +0.3 v digital inputs to dgnd . . . . . . . . . . ? 0.3 v to dv dd + 0.3 v digital outputs to dgnd . . . . . . . . . ? 0.3 v to dv dd + 0.3 v v in (+), v in ( ? ) to agnd . . . . . . . . . . ? 0.3 v to av dd + 0.3 v ref1 to agnd . . . . . . . . . . . . . . . . ? 0.3 v to av dd + 0.3 v ref2 to agnd . . . . . . . . . . . . . . . . ? 0.3 v to av dd + 0.3 v dgnd, agnd1, agnd2 . . . . . . . . . . . . . . . . . . . . . . 0.3 v input current to any pin except the supplies 2 . . . . . . . . 10 ma operating temperature range . . . . . . . . . . . ? 40 c to +85 c storage temperature range . . . . . . . . . . . . ? 65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . 72 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . 20 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional opera - tion of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents up to 100 ma will not cause scr latch-up. ordering guide package package model temperature description option AD7722as ? 40 c to +85 c 44-lead mqfp s-44b eval-AD7722cb evaluation board i ol 1.6ma i oh 200 a 1.6v c l 50pf to output pin figure 1. load circuit for timing specifications caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7722 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. b AD7722 ? timing specifications parameter symbol min typ max unit clkin frequency f clk 0.3 12.5 15 mhz clkin period (t clk = 1/f clk )t 1 0.067 0.08 3.33 s clkin low pulse width t 2 0.45 t 1 0.55 t 1 clkin high pulse width t 3 0.45 t 1 0.55 t 1 clkin rise time t 4 5ns clkin fall time t 5 5ns fsi low time t 6 2t clk fsi setup time t 7 20 ns fsi hold time t 8 20 ns clkin to sco delay t 9 40 ns sco period 1 t 10 2t clk sco transition to fso high delay t 11 410 ns sco transition to fso low delay t 12 410 ns sco transition to sdo valid delay t 13 38 ns sco transition from fsi 2 t 14 2.5 t clk sdo enable delay time t 15 30 45 ns sdo disable delay time t 16 10 30 ns drdy high time t 17 2t clk conversion time 1 t 18 64 t clk drdy to cs setup time t 19 0ns cs to rd setup time t 20 0ns rd pulse width t 21 t clk + 20 ns data access time after rd falling edge 3 t 22 t clk + 40 ns bus relinquish time after rd rising edge t 23 t clk + 40 ns cs to rd hold time t 24 0ns rd to drdy high time t 25 1t clk sync/reset input pulse width t 26 10 ns dval low delay from sync/reset t 27 40 ns sync/reset low time after clkin rising t 28 10 t clk ?10 ns drdy high delay after sync/reset low t 29 50 ns drdy low delay after sync/reset low 1 t 30 (8192 + 64) t clk dval high delay after sync/reset low 1 t 31 8192 t clk cal setup time t 34 10 ns cal pulse width t 35 12 t clk calibration delay from cal high t 36 64 t clk unipolar input calibration time, ( uni = 0) 1, 4 t 37 (3 8192 + 2 5 12) t clk bipolar input calibration time, ( uni = 1) 1, 4 t 37 (4 8192 + 3 5 12) t clk conversion results valid, ( uni = 0) 1 t 38 (3 8192 + 2 512 + 64) t clk conversion results valid, ( uni = 1) 1 t 38 (4 8192 + 3 512 + 64) t clk notes 1 guaranteed by design. 2 frame sync is initiated on falling edge of clkin. 3 with rd synchronous to clkin, t 22 can be reduced up to 1 t clk . 4 see figure 8. specifications subject to change without notice. (av dd = 5 v 5%, dv dd = 5 v 5%, agnd = dgnd = 0 v, c l = 50 pf, t a = t min to t max , f clkin = 12.5 mhz, sfmt = logic low or high, cfmt = logic low or high.)
rev. b e6e AD7722 zero for last 16 sco cycles valid data for 16 sco cycles valid clkin sco (cfmt = 0) fso (sfmt = 0) sco 32 sco cycles 64 cklin cycles figure 2a. generalized serial mode timing (fsi = logic low or high, tsi = doe) zero for last 16 sco cycles valid data for 16 sco cycles valid clkin sco (cfmt = 0) fso (sfmt = 1) sco high for last 16 sco cycles low for 16 sco cycles 64 cklin cycles 32 sco cycles figure 2b. generalized serial mode timing (fsi = logic low or high, tsi = doe) t 2 t 3 t 4 t 5 0.8v 2.3v t 8 t 1 t 6 t 7 t 9 t 9 t 10 clkin fsi sco figure 3. serial mode timing for clock input, frame sync input, and serial clock output clkin low for d15ed0 t 1 t 10 t 11 t 12 t 14 t 13 t 13 d15 d14 d13 d1 d0 d15 d14 d13 d1 d0 t 12 t 11 fsi sco fso sdo sco fso sdo sfmt = logic low(0) sfmt = logic high(1) figure 4. serial mode timing for frame sync input, frame sync output, serial clock output, and serial data output (cfmt = logic low, tsi = doe)
rev. b AD7722 e7e t 15 t 16 doe sdo figure 5. serial mode timing for data output enable and serial data output (tsi = logic low) t 17 t 20 t 21 t 23 rd db0edb15 t 22 valid data t 25 t 24 t 18 t 19 cs drdy figure 6. parallel mode read timing clkin t 29 t 30 t 31 t 27 t 26 t 28 max t 28 min sync, reset dval drdy figure 7. sync and reset timing, serial and parallel mode clkin sync, reset dval drdy 8192 t clk 8192 t clk 8192 t clk 8192 t clk 512 t clk 512 t clk 512 t clk t 38 t 34 t 37 uni = 1 t 37 uni = 0 t 35 t 36 figure 8. calibration timing, serial and parallel mode
rev. b e8e AD7722 pin function descriptions mnemonic pin no. description av dd1 14 clock logic power supply voltage for the analog modulator, 5 v 5%. agnd1 10 clock logic ground reference for the analog modulator. av dd 20, 23 analog power supply voltage, 5 v 5%. agnd 9, 13, 15, 19, ground reference for analog circuitry. 21, 25, 26 dv dd 39 digital power supply voltage, 5 v 5%. dgnd 6, 28 ground reference for digital circuitry. ref1 22 reference input/output. ref1 connects through 3 k to the output of the internal 2.5 v refer ence and to the input of a buffer amplifier that drives the - modulator. this pin can also be overdriven with an external reference 2.5 v. ref2 24 reference input/output. ref2 connects to the output of an internal buffer amplifier used to drive the - modulator. when ref2 is used as an input, ref1 must be connected to agnd. v in (+) 18 positive terminal of the differential analog input. v in ( ? )1 6n egative terminal of the differential analog input. uni i r s i uni cin c i cin d cin cin cs d i s s i s i s c c i cin rs r i rs rs rs d d i rs sync d rssync rssync cs c cs cs cin cin cs rd cs d d i cs sync s i sync d sync dc d sync d cin sync rs drdy d cin cin drdy cin d rssync rssync
rev. b AD7722 e9e pin configuration 44-lead mqfp (s-44b) 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 33 27 28 25 26 23 24 pin 1 identifier top view (not to scale) 12 13 14 15 16 17 18 19 20 21 22 AD7722 dgnd/db13 dgnd/db14 dgnd/db15 sync cs dgnd cal a gnd a gnd ref2 av dd dgnd/db2 dgnd/db1 dgnd/db0 cfmt/ drdy dval / rd dgnd uni p/ s a gnd a gnd1 clkin tsi/db3 doe/db4 sfmt/db5 fsi/db6 sco/db7 dv dd sdo/db8 fso/db9 dgnd/db10 dgnd/db11 dgnd/db12 xtal agnd av dd1 agnd v in (e) reset v in (+) agnd av dd agnd ref1 parallel mode pin function descriptions mnemonic pin no. description dval/ rd r rd cin cs cin rd cs rd d d c drdy d r drdy i drdy cin drdy sync rs dndd d s dndd d dndd d dndd d dndd d dndd d sd d sdd d scd d sid d sd d dd d sid d dndd d dndd d dndd d s
rev. b e10e AD7722 serial mode pin function descriptions mnemonic pin no. description dval/ rd d d drdy s c i sd sc c sd sc s sd sc s c sd sc s sd sc s sid s i si d si d sd si d dc si dnd dd d i d sd d si d si sd sd sd d s d dc sd d dnd si sd s d i s s s sc sc s s sid s i si d cin d sc s i d si i si d s s scd s d c cin cin sc sdd s d s sc sc s sc sd s sd d s s sc dndd i dnd dndd dndd dndd dndd dndd dndd dndd dndd
rev. b AD7722 e11e terminology signal-to-noise plus distortion ratio (s/(n+d)) s/(n+d) is the measured signal-to-noise plus distortion ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise plus distortion is the rms sum of all nonfundamental signals and harmonics to half the sampling rate (f clkin /128), excluding dc. the adc is evaluated by applying a low noise, low distortion sine wave signal to the input pins. by generating a fast fourier transform (fft) plot, the s/(n+d) data can then be obtained from the output spectrum. total harmonic distortion (thd) thd is the ratio of the rms sum of the harmonics to the rms value of the fundamental. thd is defined as thd = 20 log sqrt v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 () v 1

where v 1 is the rms amplitude of the fundamental, and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through sixth harmonics. the thd is also derived from the fft plot of the adc output spectrum. spurious-free dynamic range (sfdr) defined as the difference in db between the peak spurious or har- monic component in the adc output spectrum (up to f clkin /128 and excluding dc) and the rms value of the fundamental. normally, the value of this specification will be determined by the largest harmonic in the output spectrum of the fft. for input signals whose second harmonics occur in the stop-band region of the digital filter, a spur in the noise floor limits the sfdr. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n is equal to zero. for example, the second order terms include (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). testing is performed using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamental, expressed in db. pass-band ripple the frequency response variation of the AD7722 in the defined pass-band frequency range. pass-band frequency the frequency up to which the frequency response variation is within the pass-band ripple specification. cutoff frequency the frequency below which the AD7722 ? s frequency response will not have more than 3 db of attenuation. stop-band frequency the frequency above which the AD7722 ? s frequency response will be within its stop-band attenuation. stop-band attenuation the AD7722 ? s frequency response will not have less than 90 db of attenuation in the stated frequency band. integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are minus full scale, a point 0.5 lsb below the first code transition (100 . . . 00 to 100 . . . 01 in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode) and plus full scale, a point 0.5 lsb above the last code transition (011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to 111 . . . 11 in unipolar mode). the error is expressed in lsb. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between two adjacent codes in the adc. common-mode rejection ratio the ability of a device to reject the effect of a voltage applied to both input terminals simultaneously ? often through variation of a ground level ? is specified as a common-mode rejection ratio. cmrr is the ratio of gain for the differential signal to the gain for the common-mode signal. unipolar offset error unipolar offset error is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal differential voltage (v in (+) ? v in ( ? ) + 0.5 lsb) when operating in the unipolar mode. bipolar offset error this is the deviation of the midscale transition code (111 . . . 11 to 000 . . . 00) from the ideal differential voltage (v in (+) ? v in ( ? ) ? 0.5 lsb) when operating in the bipolar mode. gain error the first code transition should occur at an analog value 1/2 lsb above ? full scale. the last transition should occur for an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
rev. b e12e AD7722etypical performance characteristics (av dd = dv dd = 5.0 v, t a = 25 c; clkin = 12.5 mhz, ain = 20 khz, bipolar mode; v in (+) = 0 v to 2.5 v, v in (e) = 1.25 v, unless otherwise noted.) input level (db) db 110 100 50 e40 e30 0 e20 e10 90 80 70 60 sfdr s/ (n+d) tpc 1. s/(n+d) and sfdr vs. analog input level input frequency (khz) e85 e90 e115 020 100 40 60 80 e95 e100 e105 e110 thd snr sfdr v in (+) = v in (e) = 1.25v p-p v cm = 2.5v db tpc 4. snr, thd, and sfdr vs. input frequency temperature ( c) e94 e116 e50 e25 100 0255075 e96 e108 e110 e112 e114 e100 e102 e106 e104 e98 thd 3rd 4th 2nd db tpc 7. thd vs. temperature output data rate (ksps) 84 92 85 88 89 90 91 86 87 050 300 100 150 200 250 ain = 1/ 5 bw db tpc 2. s/(n+d) vs. output sample rate output data rate (ksps) 84 92 85 88 89 90 91 86 87 050 300 100 150 200 250 ain = 1/ 5 bw v in (+) = v in (e) = 1.25v p-p v cm = 2.5v db tpc 5. s/(n+d) vs. output sample rate codes frequency of occurrence 5000 0 ne3 ne2 n+3 ne1 n n+1 n+2 4500 2000 1500 1000 500 4000 3500 2500 3000 v in (+) = v in (e) clkin = 12.5mhz 8k samples tpc 8. histogram of output codes with dc input input frequency (khz) db e85 e90 e115 020 100 40 60 80 e95 e100 e105 e110 s nr sfdr thd tpc 3. snr, thd, and sfdr vs. input frequency temperature ( c) 92.0 91.5 88.0 e50 0 100 50 90.0 89.5 88.5 89.0 91.0 90.5 db tpc 6. snr vs. temperature code dnl error (lsb) 1.0 0.8 e1.0 0 20000 65535 40000 e0.4 e0.8 e0.6 0 e0.2 0.6 0.2 0.4 tpc 9. differential nonlinearity
rev. b AD7722 e13e code inl error (lsb) 1.0 0.8 e1.0 0 20000 65535 40000 e0.4 e0.8 e0.6 0 e0.2 0.6 0.2 0.4 tpc 10. integral nonlinearity error 0 e154 db e20 e80 e100 e120 e140 e40 e60 01020304050607080 98 clkin = 12.5mhz snr = 90.1db s/(n+d) = 89.2db sfdr = e99.5db thd = e96.6db 2nd = e100.9db 3rd = e106.0db 4th = e99.5db frequency (khz) tpc 11. 16k point fft 0 e154 db e20 e80 e100 e120 e140 e40 e60 020406 08096 xtal = 12.288mhz snr = 89.0db s/(n+d) = 87.8db sfdr = e94.3db thd = e93.8db 2nd = e94.3db 3rd = e108.5db 4th = e105.7db frequency (khz) tpc 12. 16k point fft clkin frequency (mhz) power (mw) 200 0 0 2.5 15.0 10.0 12.5 180 80 60 40 20 160 140 100 120 5.0 7.5 ai dd di dd tpc 13. power consumption vs. clkin frequency 0 e154 db e20 e80 e100 e120 e140 e40 e60 02040608096 ain = 90khz xtal = 12.288mhz snr = 88.1db s/(n+d) = 88.1db sfdr = e103.7db frequency (khz) tpc 14. 16k point fft 0 e154 db e20 e80 e100 e120 e140 e40 e60 02040608098 ain = 90khz clkin = 12.5 mhz snr = 89.6db s/(n+d) = 89.6db sfdr = e108.0db frequency (khz) tpc 15. 16k point fft
rev. b e14e AD7722 circuit description the AD7722 adc employs a - conversion technique that converts the analog input into a digital pulse train. the analog input is continuously sampled by a switched capacitor modulator at twice the rate of the clock input frequency, 2 f clkin . the digital data that represents the analog input is in the ones den sity of the bit stream at the output of the - modulator. the modu- lator outputs a bit stream at a data rate equal to f clkin . due to the high oversampling rate, which spreads the quantiza tion noise from 0 to f clkin /2, the noise energy contained in the band of interest is reduced (figure 9a). to reduce the quantization noise further, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest (figure 9b). the digital filter that follows the modulator provides three main functions. the filter performs sophisticated averaging on the 1-bit samples from the output of the modulator, while removing the large out of band quantization noise (figure 9c). lastly, the digital filter reduces the data rate from f clkin at the input of the filter to f clkin /64 at the output of the filter. the AD7722 output data rate, f s , is a little over twice the signal bandwidth, which guarantees that there is no loss of data in the signal band. digital filtering has certain advantages over analog filtering. first, since digital filtering occurs after the a/d conversion, it can remove noise injected during the conversion process. analog filtering cannot remove noise injected during conversion. second, the digital filter combines low pass-band ripple with a steep roll-off while also maintaining a linear phase response. b and of interest f clkin /2 digital filter cutoff frequency which equals 97.65khz (12.5mhz) b and of interest quantization noise f clkin /2 b and of interest f clkin /2 noise shaping a. b. c. figure 9. - adc the AD7722 employs two finite impulse response (fir) filters in series. the first filter is a 384-tap filter that samples the output of the modulator at f clkin . the second filter is a 151-tap half-band filter that samples the output of the first filter at f clkin /32 and decimates by 2. the implementation of this filter architecture results in a filter with a group delay of 42 conversions (84 con ver- sions for settling to a full-scale step). the digital filter provides 6 db of attenuation at a frequency (f clkin /128) one-half its output rate. with a clock frequency of 12.5 mhz, the digital filter has a pass-band frequency of 90.625 khz, a cutoff frequency is 96.92 khz, and a stop-band frequency of 104.6875 khz. due to the sampling nature of the digital filter, the filter does not provide any rejection at integer multiples of its input sampling frequency. the filter response in figure 10a shows the unattenu- ated frequency bands occurring at n f clkin where n = 1, 2, 3. . . . at these frequencies, there are frequency bands f 3 db wide (f 3 db is the ? 3 db bandwidth of the digital filter) on either side of n f clkin where noise passes unattenuated to the output. out-of-band signals coincident with any of the filter images are aliased into the pass band. however, due to the AD7722 ? s high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most broadband noise is filtered. this means that the antialias filtering requirements in front of the AD7722 are considerably reduced versus a conventional converter with no on-chip filtering. figure 10b shows the frequency response of an antialias filter. with a ? 3 db corner frequency set at f clkin /64, a single-pole filter will provide 36 db of attenuation at f clkin . depending on the application, however, it may be necessary to provide additional antialias filtering prior to the AD7722 to eliminate unwanted signals from the frequency bands the digital filter passes. it may also be necessary in some applications to provide analog filtering in front of the AD7722 to ensure that differential noise signals outside the band of interest do not saturate the analog modulator. 1f clkin 0db 2f clkin 3f clkin figure 10a. digital filter frequency response output data rate f clkin /64 0db f clkin antialias filter response required attenuation figure 10b. frequency response of antialias filter
rev. b AD7722 e15e applying the AD7722 analog input range the AD7722 uses differential inputs to provide common-mode noise rejection (i.e., the converted result will correspond to the differential voltage between the two inputs). the absolute voltage on both inputs must lie between agnd and av dd . in unipolar mode, the full-scale analog input range (v in (+) ? v in ( ? )) is 0 v to v ref2 . the output code is straight binary in the unipolar mode with 1 lsb = 38 v. the ideal transfer function is shown in figure 11. in bipolar mode, the full-scale input range is v ref2 /2. the bipolar mode allows complementary input signals. as another example, in bipolar mode, v in ( ? ) can be connected to a dc bias voltage to allow a single-ended input on v in (+) equal to v bias v ref2 /2. in bipolar mode, the output code is twos complement with 1 lsb = 38 v. the ideal transfer function is shown in figure 12. 111...111 111...110 111...101 111...100 000...011 000...010 000...001 000...000 output code 0v v ref2 e1lsb differential input voltage v in (+) e v in (e) figure 11. unipolar mode transfer function 111...111 111...110 100...001 100...000 000...010 000...001 000...000 output code 0v +v ref2 /2 e 1lsb differential input voltage v in (+) e v in (e) ev ref2 011...111 011...110 figure 12. bipolar mode transfer function differential inputs the analog input to the modulator is a switched capacitor design. the analog signal is converted into charge by highly linear sampling capacitors. a simplified equivalent circuit diagram of the analog input is shown in figure 13. a signal source driving the analog input must be able to provide the charge onto the sampling capacitors every half clkin cycle and settle to the required accuracy within the next half cycle. 18 a b a b 16 2pf 2pf ac ground 500 a b a b clkin v in (+) v in (e) AD7722 500 figure 13. analog input equivalent circuit since the AD7722 samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low common-mode noise at each input. the amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD7722. when a capacitive load is switched onto the output of an op amp, the amplitude will momentarily drop. the op amp will try to correct the situation and, in the process, will hit its slew rate limit. this nonlinear response, which can cause excessive ring ing, can lead to distortion. to remedy the situation, a low-pass rc filter can be connected between the amplifier and the input to the AD7722 as shown in figure 14. the external capacitor at each input aids in supplying the current spikes created during the sampling process. the resistor in this diagram, as well as creating the pole for the antialiasing, isolates the op amp from the tran sient nature of the load. a nalog input r c AD7722 v in (+) v in (e) r c figure 14. simple rc antialiasing circuit the differential input impedance of the AD7722 switched capacitor input varies as a function of the clkin frequency, given by the equation z f k in clkin = 10 4 9
rev. b e16e AD7722 even though the voltage on the input sampling capacitors may not have enough time to settle to the accuracy indicated by the resolu- tion of the AD7722, as long as the sampling capacitor charging follows the exponential curve of rc circuits, only the gain accuracy suffers if the input capacitor is switched away too early. an alternative circuit configuration for driving the differential inputs to the AD7722 is shown in figure 15. r 100 c 2.7nf AD7722 v in (+) v in (e) c 2.7nf c 2.7nf r 100 figure 15. differential input with antialiasing a capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one input to be effectively supplied by the other input. this minimizes undesir- able charge transfer from the analog inputs to and from ground. the series resistor isolates the operational amplifier from the current spikes created during the sampling process and provides a pole for antialiasing. the ? 3 db cutoff frequency (f 3 db ) of the antialias filter is given by equation 1, and the attenuation of the filter is given by equation 2. f rc db 3 1 6 = attenuation log f f db =+

20 1 / 1 3 2 (2) the choice of the filter cutoff frequency will depend on the a mount of roll-off that is acceptable in the pass band of the digital filter and the required attenuation at the first image fre quency. for example, when operating the AD7722 with a 12.5 mhz clock, with the typical values of r and c of 100 and 2.7 nf shown in figure 15, the ? 3 db cutoff frequency (f 3 db ) creates less than 1 db of in-band (90.625 khz) roll-off and provides about 36 db attenuation at the first image frequency. the capacitors used for the input antialiasing circuit must have low dielectric absorption to avoid distortion. film capacitors such as polypropylene, polystyrene, or polycarbonate are suitable. if ceramic capacitors are used, they must have np0 dielectric. applying the reference the reference circuitry used in the AD7722 includes an on-chip 2.5 v band gap reference and a reference buffer circuit. the block diagram of the reference circuit is shown in figure 16. the inter- nal reference voltage is connected to ref1 through a 3 k resistor and is internally buffered to drive the analog modulator ? s switched cap dac (ref2). when using the internal reference, connect 100 nf between ref1 and agnd. if the internal reference is required to bias external circuits, use an external precision op amp to buffer ref1. 24 3k AD7722 reference buffer 22 1v 2.5v reference switched-cap dac ref ref1 ref2 comparator 100nf figure 16. reference circuit block diagram the AD7722 can operate with its internal reference, or an external reference can be applied in two ways. an external reference can be connected to ref1, overdriving the internal reference. however, there will be an error introduced due to the offset of the internal buffer amplifier. for the lowest system gain errors when using an external reference, ref1 is grounded (disabling the internal buffer) and the external reference is connected to ref2. in all cases, since the ref2 voltage connects to the analog modulator, a 100 nf capacitor must connect directly from ref2 to agnd. the external capacitor provides the charge required for the dynamic load presented at the ref2 pin (figure 17). a b b 24 4pf a b a b clkin ref2 AD7722 a 4pf switched-cap dac ref 100nf figure 17. ref2 equivalent input circuit the ad780 is ideal to use as an external reference with the AD7722. figure 18 shows a suggested connection diagram. ad780 1 2 3 4 8 7 6 5 nc +v in temp gnd o/p select nc v out trim 22nf 1 f 24 ref2 AD7722 22 f 100nf 22 ref1 5v figure 18. external reference circuit connection
rev. b AD7722 e17e input circuits figures 19 and 20 show two simple circuits for bipolar mode operation. both circuits accept a single-ended bipolar signal source and create the necessary differential signals at the input to the adc. the circuit in figure 19 creates a 0 v to 2.5 v signal at the v in (+) pin to form a differential signal around an initial bias of 1.25 v. for single-ended applications, best thd performance is obtained with v in ( ? ) set to 1.25 v rather than 2.5 v. the input to the AD7722 can also be driven differentially with a complementary input, as shown in figure 20. in this case, the input common-mode voltage is set to 2.5 v. the 2.5 v p-p full-scale differential input is obtained with a 1.25 v p-p signal at each input in antiphase. this configuration minimizes the required output swing from the amplifier circuit and is useful for single-supply applications. 12pf 1k 1k 1k 12pf 1k 100nf 374k 1nf v in (e) 1/2 op275 v in (+) 18 ref1 22 ref2 100nf 24 AD7722 differential input = 2.5v p-p v in (e) bias vo lta ge = 1.25v ain = 1.25v 16 1/2 op275 1k 374k 10nf 1nf figure 19. single-ended analog input circuit for bipolar mode operation 12pf 1k ain = 0.625v 1k 1k 12pf 1k 1/2 op275 100nf r r 1nf v in (e) 1nf 1/2 op275 16 v in (+) 18 differential input = 2.5v p-p common-mode voltage = 2.5v ref1 22 op07 ref2 100nf 24 AD7722 figure 20. single-ended-to-differential analog input circuit for bipolar mode operation the 1 nf capacitors at each adc input store charge to aid the amplifier settling as the input is continuously sampled. a resistor in series with the drive amplifier output and the 1 nf input capacitor may also be used to create an antialias filter. clock generation the AD7722 contains an oscillator circuit to allow a crystal or an external clock signal to generate the master clock for the adc. the connection diagram for use with the crystal is shown in figure 21. consult the crystal manufacturer ? s recommendation for the load capacitors. 1m xtal clkin AD7722 figure 21. crystal oscillator connection an external clock must be free of ringing and have a minimum rise time of 5 ns. degradation in performance can result as high edge rates increase coupling that can generate noise in the sampling process. the connection diagram for an external clock source (figure 22) shows a series damping resistor connected between the clock output and the clock input to the AD7722. the optimum resistor will depend on the board layout and the impedance of the trace connecting to the clock input. clock circuitry clkin AD7722 25 e150 figure 22. external clock oscillator connection a low phase noise clock should be used to generate the adc sampling clock because sampling clock jitter effectively modulates the input signal and raises the noise floor. the sampling clock generator should be isolated from noisy digital circuits, grounded, and heavily decoupled to the analog ground plane. the sampling clock generator should be referenced to the analog ground plane in a split-ground system. however, this is not always possible because of system constraints. in many cases, the sampling clock must be derived from a higher frequency multipurpose system clock that is generated on the digital ground plane. if the clock signal is passed between its origin on a digital ground plane to the AD7722 on the analog ground plane, the ground noise between the two planes adds directly to the clock and will produce excess jitter. the jitter can cause degradation in the signal-to-noise ratio and can also produce unwanted harmonics. this can be remedied somewhat by transmitting the sampling clock signal as a differential one, using either a small rf trans- former or a high speed differential driver and receiver, such as the pecl. in either case, the original master system clock should be generated from a low phase noise crystal oscillator.
rev. b e18e AD7722 varying the master clock although the AD7722 is specified with a master clock of 12.5 mhz, the AD7722 operates with clock frequencies up to 15 mhz and as low as 300 khz. the input sample rate, output word rate, and frequency response of the digital filter are directly proportional to the master clock frequency. for example, reducing the clock frequency to 5 mhz leads to an analog input sample rate of 10 mhz, an output word rate of 78.125 ksps, a pass-band frequency of 36.25 khz, a cutoff frequency of 38.77 khz, and a stop-band frequency of 41.875 khz. system synchronization and control the AD7722 digital filter contains a sequencer block that controls the digital interface and all the control logic needed to operate the digital filter. a 14-bit cycle counter keeps track of where the filters are in their overall operating cycle and decodes the digital interface signals to the AD7722. the cycle counter has a number of important transition points. in particular, the bottom six bits control the convolution counter that decimates by 64 to the update rate of the output data register. the counter ? s top bit is used to provide ample time (8192 clkin cycles) to allow the modulator and digital filter to settle as the AD7722 sequences through its autocalibration process. the counter increments on the rising edge of the signal at the clkin pin and all of the digital i/o signals are synchronous with this clock. the upper bit of this counter also controls when dval or drdy sync rs c si d cin cin cin sync i sync sync d dc sync i d sync cin sync sync cin cin cin sync i d cin i drdy cin sync d d dc d d d cin cin d d d d d d cin d cin d c rs sync r i d rs sync r d
rev. b AD7722 e19e offset and gain calibration a calibration of offset and gain errors can be performed in both serial and parallel modes by initiating a calibration cycle. during this cycle, offset and gain registers in the filter are loaded with values representing the dc offset of the analog modulator and a modulator gain correction factor. the correction factors are determined by an on-chip microcontroller measuring the conver- sion results for three different input conditions: minus full scale ( ? fs), plus full scale (+fs), and midscale. in normal operation, the offset register is subtracted from the digital filter output and the result is multiplied by the gain correction factor to obtain an offset and gain corrected final result. the calibration cycle is controlled by internal logic, and the user need only initiate the cycle. a calibration is initiated when the rising edge of clkin senses a high level on the cal input. there is an uncertainty of up to 64 clkin cycles before the calibra tion cycle actually begins because the current conversion must com plete before calibration commences. the calibration values loaded into the registers only apply for the particular analog input mode (bipolar/unipolar) selected when initiating the calibration cycle. on changing to a different analog input mode, a new calibration must be performed. during the calibration cycle, in unipolar mode, the offset of the analog modulator is evaluated; the differential inputs to the modulator are shorted internally to agnd. once calibration begins, dval goes low and drdy cin cin i s r nd d cin s i s cin nd s s r r s sync rs rs c c d inrcin d i d s i d c s i d d d d d cc c d ddr dcd dd drdy cs rd r dd rd inrru ddr dsc i c cs rd drdy cin drdy drdy drdy d
rev. b e20e AD7722 serial interface the AD7722 ? s serial data interface port allows easy interfacing to industry-standard digital signal processors. the AD7722 operates solely in the master mode, providing three serial data output pins for transfer of the conversion results. the serial data clock output (sco), serial data output (sdo), and frame sync output (fso) are all synchronous with clkin. sco frequency is always one-half the clkin frequency. fso is continuously output at the conversion rate of the adc (f clkin /64). the generalized timing diagrams in figure 2 show how the AD7722 may be used to transmit its conversion results. serial data shifts out of the sdo pin synchronous with sco. the fso is used to frame the output data transmission to an external device. an output data transmission is 32 sco cycles in duration. the serial data shifts out of the sdo pin msb first, lsb last for a duration of 16 sco cycles. for the next 16 sco cycles, sdo outputs zeros. two control inputs, sfmt and cfmt, select the format for the serial data transmission. fso is either a pulse (approximately one sco cycle in duration) or a square wave with a period of 32 sco cycles, depending on the state of the sfmt. the logic level applied to sfmt also determines if the serial data is valid on the rising or falling edge of the sco. the clock format pin, cfmt, simply switches the phase of sco for the selected fso form at. with a logic low level on sfmt and cfmt set low (figure 4), fso pulses high for one sco cycle at the beginning of a data transmission frame. when fso goes low, the msb is available on the sdo pin after the rising edge of sco and can be latched on the sco falling edge. with a logic high level on sfmt and cfmt set low (figure 4), the data on the sdo pin is available after the falling edge of sco and can be latched on the sco rising edge. fso goes low at the beginning of a data transmission frame when the msb is available and returns high after 16 sco cycles. the frame sync input (fsi) can be used if the AD7722 conver- sion process must be synchronized to an external source. fsi is an optional signal; if fsi is grounded or tied high frame syncs are internally generated. frame sync allows the conversion data presented to the serial interface to be a filtered and decimated result derived from a known point in time. fsi can be applied once after power-up, or it can be a periodic signal, synchronous to clkin, occurring every 64 clkin cycles. when fsi is applied for the first time, or if a low-to-high transition is detected that is not synchronized to the output word rate, the next 127 conversions should be considered invalid while the digital filter accumulates new samples. figure 4 shows how the frame sync signal resets the serial output interface and how the AD7722 will begin to output its serial data transmission frame. a common frame sync signal can be applied to two or more AD7722s to synchronize them to a common master clock. 2-channel multiplexed operation three additional serial interface control pins (doe, tsi, and cfmt) are provided. the connection diagram in figure 24 shows how they are used to allow the serial data outputs of two AD7722s to easily share one serial data line. since a serial data transmission frame lasts 32 sco cycles, two AD7722s can share a single data line by alternating transmission of their 16-bit output data onto one sdo pin. cfmt sdo sfmt sco tsi fso fsi doe clkin AD7722 master fsi doe clkin sdo cfmt sco sfmt fso tsi AD7722 slave dv dd dv dd dgnd from control logic to host processor figure 24. connection for 2-channel multiplexed operation the data output enable pin (doe) controls sdo ? s output buffer. when the logic level on doe matches the state of the tsi pin, the sdo output buffer drives the serial dataline; otherwise, the output of the buffer goes high impedance. the serial format pin (sfmt) is set high to choose the frame sync output format. the clock format pin (cfmt) is set high so that serial data is made available on sdo after the rising edge of sco and can be latched on the sco falling edge. the master device is selected by setting tsi to a logic low and connecting its fso to doe. the slave device is selected with its tsi pin tied high, and both its fsi and doe are controlled from the master ? s fso. since the fso of the master controls the doe input of both the master and slave, one adc ? s sdo is active while the other is high impedance (figure 25). when the master transmits its conversion result during the first 16 sco cycles of a data transmission frame, the low level on doe sets the slave ? s sdo high impedance. once the master completes transmitting its conversion data, its fso goes high and triggers the slave ? s fsi to begin its data transmission frame. following power up of the two devices, once the supplies have settled, a synchronous reset/sync pulse should be issued to both adcs to ensure synchronization. after a reset/sync has been issued, fsi can be applied to the master adc to allow continuous synchronization between the processor and the adcs. for continuous synchronization, fsi should not be applied within four clkin cycles before an fso (master) edge. see figure 25. serial interfacing to dsps in serial mode, the AD7722 can be interfaced directly to several industry-standard dsps. in all cases, the AD7722 operates as the master with the dsp operating as the slave. the AD7722 outputs its own serial clock (sco) to transmit the digital word on the sdo pin to a dsp. the dsp ? s serial interface is synchronized to the data transmission provided by the fso signal. since the serial data clock from the AD7722 is always one-half the clkin frequency, dsps that can accept relatively high serial clock frequencies are required. the adsp-21xx family of dsps can operate with a maximum serial clock of 13.824 mhz; the dsp56002 allows a maximum serial clock of 13.3 mhz; the tms320c5x-57 accepts a maximum serial clock of 10.989 mhz.
rev. b AD7722 e21e to interface the AD7722 to other dsps, the master clock frequency of the AD7722 can be reduced so that the sco frequency equals the maximum allowable frequency of the serial clock input to the dsp. when the AD7722 is operated with a lower clkin frequency (< 10 mhz), dsps, such as the tms320c20/c25 and dsp56000/1, can be used. figures 26 to 28 show the interfaces between the AD7722 and several dsps. in all cases, the interface control pins, tsi, doe, sfmt, cfmt, sync, and fsi, can be permanently hardwired together to either dgnd or dv dd . alternatively, sfmt or cfmt can be tied either high or low to configure the serial data interface for the particular format required by the dsp. the frame synchronization signal, fsi, can be applied from the user ? s system control logic. fso sdo sco AD7722 rfs dr sclk adsp-21xx figure 26. AD7722 to adsp-21xx interface fso sdo sco sc1 srd sck AD7722 dsp56001/2/3 figure 27. AD7722 to dsp56000 interface fso sdo sco fsr dr clkr AD7722 tms320cxx figure 28. AD7722 to tms320c20/tms320c25/ tms320c50 interface clkin reset/sync fsi sco fso (master) fsi (slave) doe (master and slave) sdo (master) sdo (slave) t 1 t 14 note 1 t 12 t 15 t 16 note 1 t 11 t 16 t 15 d4 d3 d2 d1 d0 d15 d15 d14 d1 d0 note 1: the state of fsi cannot be changed 4 clkin cycles before a fso edge. figure 25. timing for 2-channel multiplexed operation grounding and layout the analog and digital power supplies to the AD7722 are indepen- dent and separately pinned out to minimize coupling between analog and digital sections within the device. the AD7722 should be treated as an analog component and grounded and decoupled to the analog ground plane. all the AD7722 ground pins should be soldered directly to a ground plane to minimize series induc- tance. all converter power pins should be decoupled to the analog ground plane. to achieve the best decoupling, place surface- mount capacitors as close as possible to the device, ideally right up against the device pins. the printed circuit board that houses the AD7722 should use separate ground planes for the analog and digital interface circuitry. all converter power pins should be decoupled to the analog ground plane, and all interface logic circuit power pins should be decoupled to the digital ground plane. this facili- tates the use of ground planes, which can physically separate sensitive analog components from the noisy digital system. digital and analog ground planes should only be joined in one place and should not overlap to minimize capacitive coupling between them. separate power supplies for av dd and dv dd are also highly desirable. the digital supply pin dv dd should be powered from a separate analog supply, but if necessary dv dd may share its power connection to av dd (see the connection diagram in figure 29). the 10 resistor, in series with the dv dd pin, is required to dampen the effects of the fast switching currents into the digital section of the AD7722. the ferrite is also recommended to filter high frequency signals from corrupting the analog power supply. a minimum etch technique is generally best for ground planes because it gives the best shielding. noise can be minimized by paying attention to the system layout and preventing different signals from interfering with each other. high level analog signals should be separated from low level analog signals, and both should be kept away from digital signals. in waveform sampling and reconstruction systems, the sampling clock (clkin) is as vulner- able to noise as any analog signal. clkin should be isolated from
rev. b e22e AD7722 the analog and digital systems. fast switching signals like clocks should be shielded with their associated ground to avoid radiating noise to other sections of the board, and clock signals should never be routed near the analog inputs. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the AD7722 to shield it from noise coupling. the power supply lines to the AD7722 should use as large a trace as possible (preferably a plane) to provide a low impedance path and reduce the effects of glitches on the power supply line. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. av dd 1 a gnd1 av dd a gnd av dd a gnd dv dd dgnd dgnd 100nf 100nf 100nf 1nf 10 100nf 10 f 100nf 100nf 10 f 5v 14 10 20 19 23 25 39 28 5 figure 29. power supply decoupling
rev. b AD7722 e23e outline dimensions 44-lead metric quad flat package [mqfp] (s-44b) dimensions shown in millimeters 0.80 bsc sq 0.45 0.30 2.10 2.00 1.96 2.45 max 1.03 0.88 0.73 8 0.8 seating plane top view (pins down) 1 33 34 11 12 23 22 44 coplanarity 0.10 pin 1 0.25 max 10.20 10.00 9.80 sq 14.15 13.90 13.65 compliant to jedec standards ms-022-aa-1
rev. b c01185e0e10/03(b) e24e AD7722 revision history location page 10/03?data sheet changed from rev. a to rev. b. change to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 replaced figures 7 and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 changes to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 text added to 2-channel multiplexed operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 replaced figure 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 changes to text in 2-channel multiplexed operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 changes to figure 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 change to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5/03?data sheet changed from rev. 0 to rev. a. figures and tpcs renumbered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 changes to parallel mode pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 changes to serial mode pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to differential inputs sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 changes to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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